1. Field of the Invention
The present invention generally relates to a semiconductor device and, more particularly, to a non-volatile memory device and a fabrication method thereof.
2. Description of the Related Art
As non-volatile memory devices have become more highly integrated, the need has increased for reducing the area occupied by a driving circuit for operating a memory cell. There has also been a need for an improvement in an intergate dielectric layer formed between a floating gate and a control gate such that a voltage induced to the floating gate can be maintained at a suitable level for a device's operating characteristics while a low voltage is applied to the control gate. This is so that the level of the voltage of the floating gate, which is induced when a high voltage is applied to the control gate for programming a device, is affected by a coupling ratio of the intergate dielectric layer. Accordingly, improving the coupling ratio of the intergate dielectric layer is needed.
In addition, during the process of erasing a conventional non-volatile memory device, a path of electrons is established toward a source node. That is, due to a small area through which the electrons pass, current density becomes concentrated in the area, thereby deteriorating a tunneling oxide layer, i.e., a tunneling insulating layer. Thus, a new non-volatile memory device capable of preventing deterioration of the tunneling insulating layer and having improved reliability is needed.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.